Job Title : Senior DFT Engineer Location : Santa Clara, CA (Onsite) - Relocation work Skill: [ATPG , MBIST, IO Test, Clock Verification] Experience: 5-10 years 5 Openings Required Skills & Qualifications • 4 years of hands-on experience in DFT and ATPG for SoC or ASIC designs • Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing • Proven expertise in ATPG pattern generation, analysis, and debug • Experience with MBIST, including memory test …
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