Senior SRAM Layout Design Engineer (Strategic Resourcing)

Descripción del puesto

Senior SRAM Layout Design Engineer (Strategic Resourcing) 12 Months Santa Clara, CA Role Overview Client is seeking a Senior SRAM Layout Design Engineer to own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies at the leading edge of process scaling. This is a senior individual-contributor role you'll own and contribute blocks alongside an established team of leads, not manage one. The role works closely…