Job Title: Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6 Location: San Jose, CA Position Summary: We are seeking a highly experienced Verification Lead to own the end-to-end verification of PCIe Gen5/Gen6 subsystem with Transcation Layer, Controller, PHY and Serdes. The candidate will be responsible for verification planning, methodology definition, UVM environment architecture, coverage closure, protocol compliance verification, and leadership of a team of verification eng…
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